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1 features: +3.3v core power supply +2.5v or +3.3v clock output power supply - independent clock output bank power supplies output frequency range: 6 mhz to 200 mhz bank pair output-output skew < 100 ps cycle-cycle jitter < 50 ps 50% 2% maximum output duty cycle at 100mhz eight lvttl outputs with selectable drive strength selectable positive- or negative-edge synchronization selectable phase-locked loop (pll) frequency range and lock indicator phase adjustments in 625 to 1300 ps steps up to 7.8 ns (1-6,8,10,12) x multiply and (1/2,1/4) x divide ratios compatible with spread-s pectrum reference clocks power-down mode selectable reference input divider operational environment: - total-dose tolerance: 100 krad (si) - sel immune to a let of 109 mev-cm 2 /mg - seu immune to a let of 109 mev-cm 2 /mg hirel temperature range: -55 o c to +125 o c extended industrial temp: -40 o c to +125 o c packaging options: - 48-lead ceramic flatpack - 48-lead qfndevelopment pending/contact factory standard microcircuit drawing: 5962-05214 - qml-q and qml-v compliant part introduction: the ut7r995/ut7r995c is a low-voltage, low-power, eight- output, 6-to-200 mhz clock driver. it features output phase programmability which is neces sary to optimize the timing of high-performance mi croprocessor and communication sys- tems. the user programs both the fre quency and the phase of the out- put banks through nf[1:0] and ds[1:0] pins. the adjustable phase feature allows the user to skew the outputs to lead or lag the reference clock. connect an y one of the outputs to the feedback input to achieve diff erent reference frequency multi- plication and division ratios. the devices also feature split output bank power supplies that enable banks 1 & 2, bank 3, and bank 4 to operate at a different power supply levels. the ternary pe/hd pin controls the syn- chronization of output signals to either the rising or the falling edge of the reference clock and se lects the drive strength of the output buffers. to ensure smooth startup of the ut7r995/ut7r995c, inde- pendent of the behavior of the reference clock, it is recom- mended that the pd /div pin be held low to reset the device until power up is complete and the reference clock is stable. similarly, if the frequency rang e select pin (fs) is changed during operation of the ut7r995/ut7r995c, the pd /div must be driven low for a minimum of 3 s to guarantee the transition from one fs range to the next, ensuring the reliable start up of the newly se lected pll oscillator. the ut7r995 and ut7r995c both interface to a digital clock while the ut7r995c will also interface to a quartz crystal. figure 1. 48-lead ceramic flatpack pin description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 4f0 4f1 soe pd/div pe/hd v dd v dd q3 3q1 3q0 v ss v ss v dd fb v dd v ss v ss 2q1 2q0 v dd q1 lock v ss ds0 ds1 1f0 3f1 3f0 fs v ss v ss v dd q4 4q1 4q0 v ss v ss v dd xtal1 nc/xtal2 v dd v ss v ss 1q1 1q0 v dd q1 v ss test 2f1 2f0 1f1 ut7r995 & ut7r995c standard products ut7r995 & ut7r995c radclock tm 2.5v/3.3v 200mhz high-speed multi-phase pll clock buffer datasheet august 2009
2 pd /div xtal1 3 test 33 3 pll /r pe/hd fs 3 3 /n 3 3 3 3 3 3 3 3 phase select phase select phase select and /k phase select and /m fb ds[1:0] 1f[1:0] 2f[1:0] 3f[1:0] 4f[1:0] lock 1q0 1q1 2q0 2q1 3q0 3q1 4q0 4q1 v ddq3 v ddq4 soe figure 2. ut7r995 & ut7r995c block diagram v ddq1 nc/xtal2
3 1.0 device configuration: the outputs of the ut7r995/c can be configured to run at fre- quencies ranging from 6 mhz to 200 mhz. each output bank has the ability to run at separate frequencies and with various phase skews. furthermore, numerous clock division and multi- plication options exist. the following discussion and list of tables will summarize the available configuration options for the ut7r995/c. tables 1 through 12, are relevant to the following configuration discus- sions. table 1. feedback divi der settings (n-factor) table 2. reference divider settings (r-factor) table 3. output divider settings - bank 3 (k-factor) table 4. output divider settings - bank 4 (m-factor) table 5. frequency divider summary table 6. calculating output frequency settings table 7. frequency range select table 8. multiplication factor (mf) calculation table 9. signal propagation delays in various media table 10: output skew settings table 11. pe/hd settings table 12. power supply constraints 1.1 divider configuration settings: the feedback input divider is controlled by the 3-level ds[1:0] pins as indicated in table 1 and the reference input divider is controlled by the 3-level pd /div pin as indicated in table 2. although the reference divider w ill continue to operate when the ut7r995/c is in the standard test mode of operation, the feedback divider will not be available. notes: 1. when pd /div = low, the device enters power-down mode. in addition to the reference and feedback dividers, the ut7r995/c includes output dividers on bank 3 and bank 4, which are controlled by 3f[1:0] and 4f[1:0] as indicated in ta- bles 3 and 4, respectively. notes: 1. these states are used to program the phase of the respective banks. please see equation 1 along with tables 8 and 10. notes: 1. these states are used to program the phase of the respective banks. please see equation 1 along with tables 8 and 10. each of the four divider options and their respective settings are summarized in table 5. by applying the divider options in ta- ble 5 to the calculations shown in table 6, the user determines the proper clock frequency for every output bank. table 1: feedback divider settings ( n-factor ) ds[1:0] feedback input divider - (n) permitted output divider (k or m) connected to fb ll 2 1, 2 or 4 lm 3 1, 2 or 4 lh 4 1, 2, or 4 ml 5 1 or 2 mm 1 1, 2, or 4 mh 6 1 or 2 hl 8 1 or 2 hm 10 1 hh 12 1 table 2: reference divider settings ( r-factor ) pd /div operating mode reference input divider - (r) low 1 powered down not applicable mid normal operation 2 high normal operation 1 table 3: output divider settings - bank 3 ( k-factor ) 3f(1:0) bank 3 output divider - (k) ll 2 hh 4 other 1 1 table 4: output divider settings - bank 4 ( m-factor ) 4f[1:0] bank 4 output divider (m) ll 2 other 1 1 table 5: frequenc y divider summary division factors available divider settings n 1, 2, 3, 4, 5, 6, 8, 10, 12 r1, 2 k 1, 2, 4 m1, 2
4 notes: 1. these outputs are undivided copies of the vco clock. therefore, the formulas in this column can be used to calculate the nom inal vco operating frequency (f nom ) at a given reference frequency (f xtal ) and the divider and feedback configuratio n. the user must select a configuration and a reference frequency that will generate a vco frequency that is within the range specified by fs pin. please see table 7. 1.2 frequency range and skew selection: the pll in the ut7r995/c operat es within three nominal fre- quency ranges. depending upon the desired pll operating fre- quency, the user must define th e state of the ternary fs control pin. table 7 defines the required fs selections based upon the nominal pll operati ng frequency ranges. because the clock outputs on bank 1 and bank 2 do not include a divider option, they will always reflect the cu rrent frequency of the pll. ref- erence the first column of equatio ns in table 6 to calculate the value of f nom for any given feedback clock. selectable output skew is in di screte increments of time unit (t u ). the value of t u is determined by the fs setting and the pll?s operating frequency (f nom ). use the following equation to calculate the time unit (t u ): the f nom term, which is calculated with the help of table 6, must be compatible with the nominal frequency range selected by the fs signal as defined in table 7. the multiplication factor (mf), also determined by fs, is shown in table 8. the ut7r995/c output skew steps have a typical accuracy of +/- 15% of the calculated time unit (t u ). after calculating the time unit (t u ) based on the nominal pll frequency (f nom ) and multiplication fact or (mf), the circuit designer plans routing requirements of each clock output and its respective destination receiver. with an understanding of signal propagation delays through a conductive medium (see table 9), the designer specifies trace leng ths which ensure a signal prop- agation delay that is equal to one of the t u multiples show in ta- ble 10. for each output bank, the t u skew factors are selected with the tri-level, bank-specific, nf[1:0] pins. table 6: calculating output frequency settings configuration output frequency clock output connected to fb 1q[1:0] 1 and 2q[1:0] 1 3q[1:0] 4q[1:0] 1qn or 2qn (n/r) * f xtal (n/r) * (1/k) * f xtal (n/r) * (1/m) * f xtal 3qn (n/r) * k * f xtal (n/r) * f xtal (n/r) * (k/m) * f xtal 4qn (n/r) * m * f xtal (n/r) * (m/k) * f xtal (n/r) * f xtal table 7: frequency range select fs nominal pll frequency range (f nom ) l 24 to 50 mhz m 48 to 100mhz h 96 to 200 mhz mf) * nom (f 1 u t 1. equation = table 8: mf calculation fs mf f nom examples that result in a t u of 1.0ns l 32 31.25 mhz m 16 62.5 mhz h 8 125 mhz table 9: signal propagation delays in various media medium propagation delay (ps/inch) dielectric constant air (radio waves) 85 1.0 coax. cable (75% velocity) 113 1.8 coax. cable (66% velocity) 129 2.3 fr4 pcb, outer trace 140 - 180 2.8 - 4.5 fr4 pcb, inner trace 180 4.5 alumina pcb, inner trace 240 - 270 8 - 10
5 notes: 1. nf[1:0] = ll disables bank specific outputs if test=mid and soe = high. 2. when test=mid or high, the divide-by-2, divide-by-4, and inversion- options function as defined in table 9. 3. when 4q[1:0] are set to ru n inverted (4f[1:0] = hh), soe disables these out- puts high when pe/hd = high or mid, soe disables them low when pe/hd = low. 4. skew accuracy is within +/- 15% of n*t u where "n" is the selected number of skew steps. supplied as a design limit, but not tested or guaranteed. a graphical summary of table 10 is shown in figure 3. the drawing assumes that the fb input is driven by a clock output programmed with zero skew. depending upon the state of the nf[1:0] pins the respective clocks will be skewed, divided, or inverted relative to the fedback output as shown in figure 3. 1.3 output drive, synchronization, and power supplies: the ut7r995/c employs flexible output buffers providing the user with selectable drive st rengths, independent power sup- plies, and synchronization to either edge of the reference input. using the 3-level pe/hd pin, the user selects the reference edge synchronization and the output drive strength for all clock out- puts. the options for edge synchronization and output drive strength selected by the pe/hd pin are listed in table 11. notes: 1. please refer to "dc parameters" section for i oh /i ol specifications. table 10: output skew settings 4 nf[1:0] skew 1q[1:0], 2q[1:0] skew 3q[1:0] skew 4q[1:0] ll 1, 2 -4t u divide by 2 divide by 2 lm -3t u -6t u -6t u lh -2t u -4t u -4t u ml -1t u -2t u -2t u mm zero skew zero skew zero skew mh +1t u +2t u +2t u hl +2t u +4t u +4t u hm +3t u +6t u +6t u hh 2 +4t u divide by 4 inverted 3 table 11: pe/hd settings pe/hd synchronization output drive strength 1 l negative low drive m positive high drive h positive low drive t 0 t 0 - 6t u t 0 - 5t u t 0 - 3t u t 0 - 1t u t 0 + 1t u t 0 + 2t u t 0 + 3t u t 0 + 4t u t 0 + 5t u t 0 + 6t u t 0 - 4t u t 0 - 2t u xtal1 input fb input -6t u +2t u +3t u +4t u +6t u divided -4t u -3t u -2t u -1t u 0t u +1t u inverted 1f[1:0] 2f[1:0] 3f[1:0] 4f[1:0] (n/a) (n/a) lm lm ll ll lh lh lm lm (n/a) (n/a) lh lh ml ml ml ml (n/a) (n/a) mm mm mm mm mh mh (n/a) (n/a) hl hl mh mh hm hm (n/a) (n/a) hh hh hl hl (n/a) (n/a) hm hm (n/a) (n/a) ll/hh ll (n/a) (n/a) (n/a) hh figure 3. typical outputs with fb connected to a zero-skewed output
6 when the outputs are configured for low drive operation, they will provide a minimum 12ma of drive current regardless of the selected output power supply. if the outputs are configured for high drive operation, they will provide a minimum 24ma of drive current under a 3.3v power supply and 20ma when pow- ered from a 2.5v supply. the ut7r995/c features split power supply buses for banks 1 and 2, bank 3, and bank 4. these independent power supplies enable the user to obtain both 3.3v and 2.5v output signals from one ut7r995/c device. the core power supply (v dd ) must run from a 3.3v power supply. table 12 summarizes the various power supply options available with the ut7r995/c. notes: 1. v dd q1/3/4 must not be set at a level higher than that of v dd . 1.4 reference clock interfaces when an external, lvcmos/lv ttl, digital clock is used to drive the ut7r995 and ut7r995c, the reference clock signal should drive the xtal1 input of the radclock, while the xtal2 output should be left unconnected (see figure 4). note, for the ut7r995 only, the xtal2 pin is defined as a no- connect. in addition to a digital clock reference, the ut7r995c can in- terface to a quartz crystal. when interfacing to a quartz crystal, xtal1 and xtal2 are the input and output, respectively, of an inverting amplifier within the radclock. this inverting am- plifier provides the initial 180 o phase shift of the reference clock whose frequency, and subsequent 180 o phase shift, is set by the quartz crystal and its surrounding rlc network. figure 5 shows a typical pierce-oscillat or with tank-circuit that will support reliable startup of fund amental and odd-harmonic, at- cut, quartz crystals. table 12: power supply constraints 1 v dd v dd q1 v dd q3 v dd q4 3.3v 3.3v or 2.5v 3.3v or 2.5v 3.3v or 2.5v n/c external digital oscillator nc/xtal2 xtal1 v ss figure 4. external digital clock oscillator interface figure 5. pierce crystal osci llator with tank circuit y1 rdc r1 c1 c2 l1 cdc xtal1 xtal2 ut7r995c fundamental frequency pierce crystal oscillator rdc = ~10m ; l1 = not used; cdc = not used c2 is used to tune the circ uit for stable oscillation. typical values for c2 range from 30pf to 50pf. r1 and c1 are selected to create a time constant that facilitates the funda- mental frequency (f f ) of the quartz crystal as defined in equation 2. as an example, selecting a value of 100 for r1 and 80pf for c1 would fa- cilitate the reliable operation of a 20mhz, at-cut, quartz crystal. higher frequency pierce crystal oscillator rdc = ~10m ; cdc = ~1.5nf; c2 = tuning capacitor similar to prior example r1 and c1 are selected to create a time constant that facilitates the overtone frequency (f ot ) of the quartz crystal as shown in equation 3. additionally, l1 is selected such that its relationship with c1 facilitates a frequency falling between the fundamental frequency (f f ) and the specified overtone frequency (f ot ) of the quartz crystal as shown in equation 4. as an example, selecting the followi ng component values will result in a 50mhz pierce crystal oscillator based upon an 3rd overtone, at-cut, quartz crystal having a fundamental frequency of 16.6666mhz. rdc = 10m ; cdc = 1.5nf; c2 = 30pf; r1 = 50 ; c1 = 55pf; l1 = 300nh f f = 16.6666mhz; f ot = 50mhz () 1 * 1 * 2 1 c r f f = equation 2. equation 3. () 1 * 1 * 2 1 c r f ot = () 1 * 1 * 2 1 c l f m = equation 4.
7 3.0 pin description flatpack pin no. name i/o type description 37 xtal1 i lvttl primary reference clock input. when interfacing a single-ended reference clock to the ut7r995 or ut7r995c, this input must be driven by an lvttl/lvcmos clock source. if a quartz crystal is used as the refe rence clock source (ut7r995c only), the second pin on the crystal must be connected to xtal2. if a singled ended reference clock is supplied to this pin, then xtal2 should be left unconnected. 36 n/c -- -- no connect. ut7r995 only. xtal2 o n/a feedback output from the on-board crystal oscillator. when a crystal is used to supply the reference clock for the ut7r995c, this pin must be connected to the second terminal of the quartz crystal. if a single-ended reference clock is supplied to xtal1, then this output should be left unconnected. 13 fb i lvttl feedback input for the pll. when fb is not driven by an active clock output the pll will run to its maximu m frequency, unless the device is placed in power-down. 28 test 1 i 3-level built-in test control signal. when test is set to the mid or high level, it disables the pll and the xtal1 reference frequency is driven to all outp uts (except for the conditions described in note 1). set test low for normal operation. 2.0 opeational environment table 13: operational environment notes: 1. the ut7r995/c are latchup immune to particle lets >109 mev-cm 2 /mg. 2. worst case temperature and voltage of t c = +125 o c, v dd = 3.6v, v dd q1/q3/q4 = 3.6v for sel. 3. worst case temperature and voltage of t c = +25 o c, v dd = 3.0v, v dd q1/q3/q4 = 3.0v for seu. 4. all seu data specified in this datasheet is base d on the storage elements used in the ut7r995/c. 5. for characterization data on the ut7r 995/c set performance over allowable opera ting ranges, please contact the factory. parameter limit units total ionizing dose (tid) >1e6 rads(si) single event latchup (sel) 1, 2 >109 mev-cm 2 /mg onset single event upset (seu) let threshold 3, 4 >109 mev-cm 2 /mg onset single event transient (set ) let threshold (@ 50mhz; fs=l) 5 >74 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2
8 3soe ilvttl synchronous output enable. the soe input is used to synchronously enable/ disable the output clocks. each clock output that is controlled by the soe pin is synchronously enabled/disabled by the individual output clock. when high , soe disables all clocks except 2q0 and 2q1. when disabled, 1q0, 1q1, 3q0, and 3q1 will always enter a low state when pe/hd is mid or high , and they will disable into a high state when pe/hd is low . the disabled state of 4q0 and 4q1 is dependent upon the state of pe/hd and 4f[1:0]. the following table illustrates the disabl ed state of bank 4 outputs as they are controlled by the state of pe/hd and 4f[1:0]. pe/hd 4f[1:0]* 4q0 4q1 low hh low low mid hh high high high hh high high *all other combinations of 4f[1:0] will result in 4q0 and 4q1 disabling into a low state when pe/hd is mid or high , and they will disable into a high state when pe/hd is low . when test is held at the mid level and soe is high , the nf[1:0] pins act as individual output enable/disable controls for each output bank, excluding bank 2. setting both nf[1:0] signals low disables the corresponding output bank. set soe low to place the ut7r995/c radclock tm outputs into their normal operating modes. 1, 2, 24, 25, 26, 27, 47, 48 nf[1:0] i 3-level output divider and ph ase skew selection fo r each output bank. please see tables 3, 4, 5, 6, and 9 for a complete explanation of the nf[1:0] control functions and their effects on output frequency and skew. 46 fs i 3-level vco operating freque ncy range selection. please see tables 7 and 8. 8, 9, 17, 18, 31, 32, 41, 42 nq[1:0] o lvttl four clock banks of two outputs each. please see table 6 for frequency settin gs and table 9 for skew settings. 22, 23 ds[1:0] i 3-level feedback input divider selection. please see table 1 for a summary of th e feedback input divider settings. 5 pe/hd i 3-level positive/negative edge cont rol and high/low output drive strength selection. the pe portion of this pin controls which edge of the reference input synchronizes the clock outputs. the hd portion of this pin controls the drive strength of the output clock buffers. the following table summari zes the effects of the pe/hd pin during normal operation. pe/hd synchronization output drive strength low negative edge low drive mid positive edge high drive high positive edge low drive low drive strength outputs provide 12ma of drive strength while the high drive condition results in 24ma of current drive. output banks operating from a 2.5v power supply guarantee a high drive of 20ma. flatpack pin no. name i/o type description
9 4pd /div i 3-level power down and reference divider control. this dual function pin controls the power down operation and selects the input reference divider. holding the pin low during power up ensures clean radclock startup that is independent of the behavior of the reference clock. the pin may also be driven low at any ti me to force a reset to the pll. the following table summarizes the operating states controlled by the pd /div pin. pd /div operating mode input reference divider low powered down n/a mid normal operation 2 high normal operation 1 20 lock o lvttl pll lock indica tion signal. a high state indicates that the pll is in a locked condition. a low state indicates that the pll is not locked and the outputs may not be synchronized to the input. as the following table indicates, the level of phase alignment between xtal1 and fb that will cause the lock pin to change states is dependent upon the frequency range selected by the fs input. fs lock resolution l 1.6ns typical m 1.6ns typical h 800ps typical ** note: the lock pin can only be consid ered as a valid outp ut when the radclock is in a normal mode of operation (e.g. pd /div != low, test = low, and a valid reference clock is supplied to the xtal1 input). until these conditions are met, radclock is not in a normal operating mode and the lock pin may be high or low and therefore should not be used in making any logical decisions until the device is in a normal operating mode. reference the t lock parameter in the ac timing specification to determine the delay fo r the lock pin to become valid high following a stable input reference clock and the application of a clock to the fb input. 43 v dd q4 2 pwr power power supply for bank 4 output buffers. please see table 12 for supply level constraints. 7 v dd q3 2 pwr power power supply for bank 3 output buffers. please see table 12 for supply level constraints. 19, 30 v dd q1 2 pwr power power supply for bank 1 and bank 2 output buffers. please see table 12 for supply level constraints. 6, 12, 14, 35, 38 v dd 2 pwr power power supply for internal circuitry. please see table 12 for supply level constraints. 10, 11, 15, 16, 21, 29, 33, 34, 39, 40, 44, 45 v ss pwr power ground flatpack pin no. name i/o type description notes: 1. when test = mid and soe = high, the pll remains active with nf[1:0] = ll functioning as an output disable control for individual output banks. skew selections remain in effect unless nf[1:0] = ll. 2. a bypass capacitor (0.1 f) should be placed as close as possible to each positive power pin (<0.2"). an additional 1 f capacitor should be located within 0.2" of the output bank power supplies (v dd q1, v dd q3, and v dd q4). if these bypass capacitors ar e not close to the pins, their hi gh frequency filtering character- istics will be cancelled by the parasitic inductance of the trac es. additionally, it is recommend that wide traces (0.025" or w ider) be used wh en connecting the decoupling capacitors to their respec tive power pins on the radclock.
10 4.0 absolute maximum ratings: 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may caus e permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the oper ational sections of this spec ification is not recommended. exposure to absolute maximum rating conditions for extended periods may aff ect device reliability and performance. 2. maximum junction temperat ure may be increased to +175 c during burn-in an d steady-static life. 5.0 recommended operating conditions: symbol description limits units v dd core power supply voltage -0.3 to 4.0 v v dd q1, v dd q3, and v dd q4 output bank power supply voltage -0.3 to 4.0 v v in voltage any input pin -0.3 to v dd + 0.3 v v out voltage any clock bank output -0.3 to v dd qn + 0.3 v v o voltage on xtal2 and lock outputs -0.3 to v dd + 0.3 v i i dc input current + 10 ma p d maximum power dissipation 1.5 w t stg storage temperature -65 to +150 c t j maximum junction temperature 2 +150 c jc thermal resistance, junction to case 15 c/w esd hbm esd protection (human body model) - class ii 3000 v symbol description limits units v dd core operating voltage 3.0 to 3.6 v v dd q1, v dd q3, and v dd q4 output bank operating voltage 2.25 to 3.6 v v in voltage any configuration and control input 0 to v dd v v out voltage any bank output 0 to v dd qn v t c case operating temperature -55 to +125 c
11 6.0 dc input electrical characteristi cs (pre- and post-radiation)* (v dd = +3.3v + 0.3v; t c = -55 c to +125 c) (for "w" screening, t c = -40 c to +125 c) notes: * post-radiation perform ance guaranteed at 25 c per mil-std-883 method 1019, condition a up to a tid level of 1.0e6 rad(si). 1. these inputs are normally wired to v dd , v ss , or left unconnected. inte rnal termination resistors bi as unconnected inputs to v dd /2 + 0.3v. the 3-level inputs include: test, pd /div, pe/hd, fs, nf[1:0], ds[1:0]. 2. capacitance is measured for initial qualification and when de sign changes may affect the input/output capacitance. capacitan ce is measured between the designated terminal and v ss at a frequency of 1mhz and a sign al amplitude of 50mv rms maximum. 3. pin fs is guaranteed by functional testing. 4. for pin fb, this specification is supplied as a de sign limit, but is neither guaranteed nor tested. symbol description conditions min. max. units v ih 4 high-level input voltage (xtal1, fb and soe inputs) 2.0 -- v v il 4 low-level input voltage (xtal1, fb and soe inputs) -- 0.8 v v ihh 1, 3 high-level input voltage v dd - 0.6 -- v v imm 1, 3 mid-level input voltage v dd 2 - 0.3 v dd 2 + 0.3 v v ill 1, 3 low-level input voltage -- 0.6 v i il input leakage current (xtal1, fb and soe inputs) v in = v dd or v ss; v dd = max -5 5 a i 3l 1 3-level input dc current high, v in = v dd -- 200 a mid, v in = v dd /2 -50 50 a low, v in = v ss -200 -- a i ddpd power-down current v dd = v dd qn = +3.0v; test & soe = high; xtal1, pd /div, fb, fs, & pe/ hd = low; all other inputs are floated; outputs are not loaded t c = + 25 c -- 100 a t c = +1 25 c -- 150 a t c = - 55 c -- 4.5 ma c in-2l 2 input pin capacitance 2-level inputs f = 1mhz @ 0v; v dd = max 8.5 pf c in-3l 2 input pin capacitance 3-level inputs f = 1mhz @ 0v; v dd = max 15 pf
12 7.0 dc output electrical character istics (pre- and post-radiation)* (v dd qn = +2.5v + 10%; v dd = +3.3v + 0.3v; t c = -55 c to +125 c) (for "w" screening, t c = -40 c to +125 c) (note 1) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019, condition a up to a tid level of 1.0e6 rad(si). 1. unless otherwise noted, these tests are performed with v dd and v dd qn at their minimum levels. 2. supplied as a design limit. neither guaranteed nor tested. 3. when measuring the dynamic supply current, all outputs are loaded in accordance with the equivalent test load defined in fig ure 10. 4. capacitance is measured for initial qua lification and when design ch anges may affect the input/output capacitance. capacitan ce is measured between the designated terminal and v ss at a frequency of 1mhz and a si gnal amplitude of 50mv rms maximum. 5. for the ut7r995, the 200mhz test conditio n is based on an xtal1 frequency of 200mhz . for the ut7r995c, th e 200mhz test condi tion is based on an xtal1 frequency of 16.666667mhz, an d a n-divider setting of 12. 6. to reduce power consumption for the device, the user may tie the unused v dd qn pins to v ss . symbol description conditions min. max. units v ol output low voltage i ol = 12ma (pe/hd = low or high); (pins: nq[1:0]) -- 0.4 v i ol = 20ma (pe/hd = mid); (pins: nq[1:0]) -- 0.4 v i ol = 2ma (pins: lock) -- 0.4 v i oh = -6ma (pe/hd=loworhigh); (pins: nq[1:0]; v dd qn = +2.25v) 2.0 -- v v oh high-level output voltage i oh = -10ma (pe/hd=lowor high ); (pins: nq[1:0]; v dd qn = +2.375v) 2.0 -- v i oh = -10ma (pe/hd = mid); (pins: nq[1:0]; v dd qn = +2.25v) 2.0 -- v i oh = -20ma (pe/hd = mid); (pins: nq[1:0]; v dd qn = +2.375v) 2.0 -- v i oh = -2ma (pins: lock) 2.4 -- v i os qn 2 short-circuit output current v o = v dd qn or v ss ; v dd qn = +2.75v; pe/hd = mid -500 500 ma v o = v dd qn or v ss ; v dd qn = +2.75v; pe/hd = low or high -300 300 ma i ddop 3,5,6 dynamic supply current @200mhz (fs = high); v dd = max; v dd qn = +2.75v; c l = 20pf/output ut7r995 -- 200 ma ut7r995c -- 280 ma @50mhz (fs = low); v dd = max; v dd qn = +2.75v; c l = 20pf/output ut7r995 -- 130 ma ut7r995c -- 145 ma c out 4 output pin capacitance f = 1mhz @ 0v; v dd = max; v dd qn = +2.75v 15 pf
13 7.0 dc output electrical characteris tics (pre- and post-radiation)* (v dd qn = +3.3v + 0.3v; v dd = +3.3v + 0.3v; t c = -55 c to +125 c) (for "w" screening, t c = -40 c to +125 c) (note 1) notes: * post-radiation perform ance guaranteed at 25 c per mil-std-883 method 1019, condition a up to a ti d level of 1.0e6 rad(si). 1. unless otherwise noted, thes e tests are performed with v dd and v dd qn at their minimum levels. 2. supplied as a design limit. neither guaranteed nor tested. 3. when measuring the dynamic supply current, all outputs are loaded in accordance with the equivalent test load defined in fig ure 10. 4. capacitance is measured for initial qualification and when de sign changes may affect the input/output capacitance. capacitan ce is measured between the designated terminal and v ss at a frequency of 1mhz and a si gnal amplitude of 50mv rms maximum. 5. for the ut7r995, the 200mhz test condition is based on an xtal1 frequency of 200mhz. for the ut7r995c, the 200mhz test condi tion is based on an xtal1 frequency of 16.666667mhz, an d a n-divider setting of 12. 6.to reduce power consumption for the device, the user may tie the unused v dd qn pins to v ss. symbol description conditions min. max. units v ol output low voltage i ol = 12ma (pe/hd = low or high); (pins: nq[1:0]) -- 0.4 v i ol = 24ma (pe/hd = mid); (pins: nq[1:0]) -- 0.4 v i ol = 2ma (pins: lock) -- 0.4 v v oh high-level output voltage i oh = -12ma (pe/hd = low or high); (pins: nq[1:0]) 2.4 -- v i oh = -24ma (pe/hd = mid); (pins: nq[1:0]) 2.4 -- v i oh = -2ma (pins: lock) 2.4 -- v i os qn 2 short-circuit output current v o = v dd qn or v ss ; v dd qn = +3.6v; pe/hd = mid -600 600 ma v o = v dd qn or v ss ; v dd qn = +3.6v; pe/hd = low or high -300 300 ma i ddop 3,5,6 dynamic supply current @200mhz (fs = high); v dd = max; v dd qn = +3.6v; c l = 20pf/output ut7r995 -- 250 ma ut7r995c -- 360 ma @50mhz (fs = low); v dd = max; v dd qn = +3.6v; c l = 20pf/output ut7r995 -- 150 ma ut7r995c -- 160 ma c out 4 output pin capacitance f = 1mhz @ 0v; v dd = max; v dd qn = +3.6v 15 pf
14 8.0 ac input electrical characteristics (pre - and post-radiation)* (v dd = v dd qn = +3.3v + 0.3v; t c = -55 c to +125 c) (note 1) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. reference figure 11 for clock output load ing circuit that is equivalent to the load circuit used for all ac testing. the inp ut waveform used to test these parameters is shown in figure 9. 2. supplied only as a design guidelin e, neither tested nor guaranteed. 3. when driving the ut7r995c with a crystal, the xtal1 pin does not define maximum input rise/fall time. 4. although the input reference frequencies ar e defined as-low-as 2mhz, the n and r divide rs must be selected to ensure the pll operates from 24mhz-50mhz when fs = low, 48mhz-100mhz when fs = mi d, and 96mhz-200mhz when fs = high. 5. the ut7r995c is guaranteed by charact erization for quartz crystal frequencies ranging from 2mhz to 48mhz. contact the factor y for support using quartz crystals that oscillate above 48mhz. 6. for the ut7r995c only, this parameter is guaranteed by characterization, but not tested. 7. for the ut7r995c only, this parameter is guaranteed by ch aracterization, but only tested for frequencies <100 mhz. symbol description condition min. max. unit t r , t f 2, 3 input rise/fall time vih(min)-vil(max) -- 20 ns/v t pwc 6 input clock pulse high or low 2 -- ns t xtal 7 input clock period 1 f xtal 5 500 ns t dcin 6 input clock duty cycle high or low 10 90 % f xtal 4, 5, 7 digital referenc e input frequency fs = low; pd /div = high 2 50 mhz fs = low; pd /div = mid 4 100 mhz fs = mid; pd /div = high 4 100 mhz fs = mid; pd /div = mid 8 200 mhz fs = high; pd /div = high 8 200 mhz fs = high; pd /div = mid 16 200 mhz
15 9.0 ac output electrical characteris tics (pre- and post-radiation)* (v dd = +3.3v + 0.3v; t c = -55 c to +125 c) (for "w" screening, t c = -40 c to +125 c) (note 1) symbol description condition min. max. unit f or output frequency range v dd qn = +3.3v 6 200 mhz vco lr vco lock range v dd qn = +3.3v 24 200 mhz vco lbw 2 vco loop bandwidth v dd = v dd qn = +3.3v; t c = room temperature 0.25 3.5 mhz t skewpr 3, 8 matched-pair skew skew between the earliest and the latest output transitions within the same bank. -- 100 ps t skew0 3, 8 output-output skew skew between the earliest and the latest output transitions among all outputs at 0t u . -- 200 ps t skew1 3 skew between the earliest and the latest output transitions among all outputs for which the same phase delay has been selected. -- 200 ps t skew2 3 skew between the nominal output rising edge to the inverted output falling edge -- 500 ps t skew3 3 skew between non-inverted outputs running at different frequencies. -- 500 ps t skew4 3 skew between nominal to inverted outputs running at different frequencies. -- 600 ps t skew5 3 skew between nominal outputs at different power supply levels. -- 650 ps t part 8 part-part skew skew between the outputs of any two devices under identical settings and conditions (v dd qn, v dd , temp, air flow, frequency, etc). -- 450 ps t pd0 4, 8 xtal1 to fb propagation delay v dd = v dd qn = +3.3v; t c = room temperature -250 +250 ps t odcv 8 output duty cycle fout < 100 mhz, measured at v dd 2 48 52 % fout > 100 mhz, measured at v dd 2 45 55 % t pwh output high time deviation from 50% measured at 2.0v; v dd qn = +3.3v -- 1.5 ns t pwl output low time deviation from 50% measured at 0.8v; v dd qn = +3.3v -- 2.0 ns t orise 8 & t ofall output rise/fall time measured as transition time between v oh = +1.7v and v ol = +0.7v for v dd = 3.0v; v dd qn = +2.25v; c l = 40pf pe/hd = high 0.30 1.5 ns pe/hd = mid 0.25 1.25 ns measured as transition time between v oh = +2.0v and v ol = +0.8v for v dd = 3.6v; v dd qn = +3.3v; c l = 40pf pe/hd = high 0.20 1.25 ns pe/hd = mid 0.10 1.0 ns t lock 5 pll lock time -- 0.5 ms t lockres 2, 6 lock pin resolution fs = low 1.6ns + 200ps typ. ns fs = mid 1.6ns + 200ps typ. ns fs = high 800ps + 100ps typ. ps
16 notes: 1. reference figure 11 for clock output lo ading circuit that is equivalent to th e load circuit used for all ac testing. 2. supplied as a design guideline. neither guaranteed nor tested. 3. test load = 40pf, terminated to v dd 2. all outputs are equally loaded. see figure 11. 4. t pd is measured at 1.5v for v dd = 3.3v with xtal1 rise/fall times of 1ns between 0.8v-2.0v. 5. t lock is the time that is required be fore outputs synchronize to xtal1 as determined by the phase alignment be tween the xtal1 and fb inputs. this specification is valid with stable power supplies wh ich are within normal operating limits. 6. lock detector circuit will monitor the phase alignment between the xtal1 and fb in puts. when the phase separation between th ese two inputs is greater than the amount listed, then the lock pin will drop low signaling that the pll is out of lock. 7. this parameter is guaranteed by measuring cycl e-cycle jitter on 55,000, ba ck-to-back clock cycles. 8. guaranteed by characterization, but not tested. t ccj 7 cycle-cycle jitter divide by 1 output frequency, fb = divide by 12 -- 50 ps symbol description condition min. max. unit
17 xtal1 fb nq0 nq1 inverted q xtal1 2 xtal1 4 t xtal t pwc t pd0 t odcv t dcin t odcv t ccj(1-12) t skewpr t skew0, t skew1 t skew2 t skew4 t skew3 t skew5 (v dd qn = 2.5v) (v dd qn = 3.3v) figure 6. ac timing diagram
18 figure 10. output test load ci rcuit for lock and dynamic power supply current measurements 2.0v 0.8v v th = 1.5v t pwh t pwl t orise t ofall figure 7. +3.3v lvttl output waveform 1.7v 0.7v v th = 1.25v t pwh t pwl t orise t ofall figure 8. +2.5v lvttl output waveform 2.0v 0.8v v th = 1.5v < 1ns < 1ns figure 9. +3.3v lvttl input test waveform 3.0v 0v c l 150 150 : v dd qn d ut figure 11. clock output ac test load circuit 100 100 c l dut note: this is not the recommended termination for normal user operation.
19 notes: 1. all exposed metallized areas are gold plated over electrically plated nickel per mil-prf- 38535. 2. the lid is electrically connected to v ss . 3. lead finishes are in accordance with mil- prf-38535. 4. dimension symbology is in accordance with mil-prf-38535. 5. lead position and coplanarity are not measured. 6. id mark symbol is vendor option: no alphanumerics. figure 12. 48-lead ceramic
20 ordering information ut7r995 and ut7r995c: lead finish (notes 1 & 2): (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) screening (notes 3, 4 & 5): (c) = hirel temperature range flow (-55 c to +125 c) (p) = prototype flow (w) = extended industrial temperature range flow (-40 c to +125 c ) (j) = commercial termperature range flow (0 o c to +70 o c) package type: (x) = 48-lead ceramic flatpack notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part marking will match the lead fini sh and will be either ?a? (solder) or ?c? (gold). 3. prototype flow per utmc manufacturing flows document. tested at 25 c only. lead finish is gold only. ra diation neither tested nor guaranteed. 4. hirel temperature range flow per aero flex colorado springs manufacturing flow s document. devices are tested at -55 c, room temp, and 125 c. radiation neither tested nor guaranteed. 5. commercial temperature range flow only performed for package type y, 48-lead qfn. ut7r995 - * * * lead finish (notes 1 & 2): (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) screening (notes 3, 4 & 5): (c) = hil rel temperature range flow (-55 c to +125 c) (p) = prototype flow (w) = extended industrial temperature range flow (-40 c to +125 c) (j) = commercial termpe rature range flow (0 o c to +70 o c) package type: (x) = 48-lead ceramic flatpack ut7r995c - * * *
21 ut7r995 and ut7r995c: smd lead finish (notes 1 & 2): (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) case outline: (x) = 48-lead ceramic flatpack class designator: (q) = qml class q (v) = qml class v device type (01) = ut7r995 -> 6mhz-to-200mhz , high speed, multi-phase, zero-d elay, without crystal capability (02) = ut7r995 - extended industrial temperature (-40 c to +125 c ) (03) = ut7r995c -> 6mhz-t o-200mhz, high speed, multi-phase, ze ro-delay, with crystal capability (04) = ut7r995c - extended industrial temperature (-40 c to +125 c ) drawing number: 5962-05214 total dose (note 3): (r) = 1e5 rads(si) (f) = 3e5 rads(si) (note 4) (g) = 5e5 rads(si) (note 4) (h) = 1e6 rads(si) (note 4) federal stock class designator: no options notes: 1.lead finish (a,c, or x) must be specified. 2.if an ?x? is specified when ordering, part marking will match the lead finish and will be eith er ?a? (solder) or ?c? (gold). 3.total dose radiation must be specified when ordering. qm l q and qml v are not available without radiation hardening. 4.these radiation screen levels are currently unavailable. cont act the factory for in formation rega rding lead-time and availabi lity. 5962 * 05214 ** * * *
22 colorado toll free: 800-645-8862 fax: 719-594-8468 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs, inc., reserves the right to make changes to any products and services herein at any time without notice. consult aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a pr oduct or service from aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. aeroflex colorado springs - datasheet definition advanced datasheet - product in development preliminary datasheet - shipping prototype datasheet - shipping qml & reduced hirel

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